1. Field
The present invention relates to a semiconductor memory having memory cells and a memory system having the semiconductor memory and a controller.
2. Description of the Related Art
In a semiconductor memory such as a DRAM, a memory cell is connected to one of a pair of complementary bit lines via a transfer gate operating in accordance with a voltage of a word line. In a read operation, data retained in the memory cell is output to one of the pair of bit lines. The other of the bit lines is set to a precharge voltage before the read operation. Then, a voltage difference between the pair of bit lines is amplified by a sense amplifier and output as read data. Generally, the bit lines are set to the precharge voltage and the word lines to a ground voltage or the like during standby of the DRAM.
When, for example, a failure occurs due to a short circuit between a word line and a bit line, the bad word line is replaced by a redundant word line. Alternatively, a bad bit line pair is replaced by a redundant bit line pair. However, the short circuit between the word line and the bit line physically remains even after the failure is relieved. Thus, a leak current still flows to a ground line from a precharge voltage line via a short circuit portion after the failure is relieved. If a leak current is large in a DRAM, the DRAM will be removed as a defective component.
In order to reduce standby current failure accompanying a short circuit between a word line and a bit line, a technique to arrange a resistor element between a precharge voltage line and a bit line has been proposed (for example, Japanese Unexamined Patent Application Publication No. Hei 8-263983). A technique to arrange a resistor element between a precharge voltage line and a sense amplifier has also been proposed (for example, Japanese Unexamined Patent Application Publication No. Hei 11-149793). Further, a technique to connect a precharge voltage line to a bit line and a sense amplifier only a certain period before activating a word line has been proposed (for example, Japanese Unexamined Patent Application Publication No. Hei 4-47588 and Japanese Unexamined Patent Application Publication No. Hei 6-52681).
However, when a resistor element is arranged between a precharge voltage line and a bit line or between a precharge voltage line and a sense amplifier, a precharge operation will be slower and an access cycle time longer as a resistance value is increased to reduce a leak current.
Moreover, in a semiconductor memory such a DRAM, the number of sense amplifiers is reduced to reduce the chip size by making memory blocks adjacent to each other share the sense amplifier. However, no method of reducing a leak current accompanying a short circuit between a word line and a bit line in a shared sense amplifier type semiconductor memory has been proposed.